Execution Excellence

 ICpedia participated in the design and verification of HSIC USB IP. HSIC removes the analog transceivers found in normal USB.
HSIC uses 2 signals (strobe, data) in a source synchronous serial interface with 240MHz DDR signaling to provide a 480Mbps USB interface. The electrical interface uses 1.2 volt LVCMOS logic levels. Both Data and strobe are bi-directional utilizing NRZI encoding. 

 ICpedia participated in the design and verification of the HDMI PHY.  The HDMI interface supplies both high-definition video, multi-channel, digital audio for consumer Audio Visual [AV] entertainment equipment [HDTV, Amplifiers, DVD, TVs], and Control Signals. The HDMI interface is all digital, with no analog signals. HDMI is backward compatible with the DVI interface, but without the more advanced upgrades and no audio. The two main buses that comprise the HDMI interface are the; Transition Minimized Differential Signaling (TMDS) and Consumer Electronics Control (CEC). 

Serial ATA (SATA, abbreviated from Serial AT Attachment) is a Computer bus interface that connects host bus adapters  to mass storage devices  such as hard disk drives, optical drives, and solid-state drives. Serial ATA succeeded the older Parallel ATA (PATA) standard, offering several advantages over the older interface: reduced cable size and cost (seven conductors instead of 40 or 80), native hot swapping, faster data transfer  through higher signaling rates, and more efficient transfer through an (optional) I/O queuing protocol. 

The XAUI is a low pin count, self-clocked serial bus directly evolved from Gigabit Ethernet. The XAUI interface speed is 2.5 times that used in Gigabit Ethernet. By arranging four serial lanes, the 4-bit XAUI interface supports the ten-times data throughput required by 10 Gigabit Ethernet. The XAUI employs the same robust 8B/10B transmission code of Gigabit Ethernet to provide a high level of signal integrity through the copper media typical of chip-to-chip printed circuit board traces. Additional benefits of XAUI technology include its inherently low EMI (Electro-Magnetic Interference) due to its self-clocked nature, compensation for multi-bit bus skew—allowing  significantly longer-distance chip-to-chip—error detection and fault isolation capabilities, low power consumption, and the ability to integrate the XAUI input/output within commonly available CMOS processes.

USB 3.0 is a Universal Serial Bus standard. Most new computers and devices being manufactured today support USB 3.0. USB 3.0 is often referred to as SuperSpeed USB.

Devices that adhere to the USB 3.0 standard can theoretically transmit data at a maximum rate of 5 Gbps. This is in stark contrast to previous USB standards, like USB 2.0, that at best can only transmit data at 480 Mbps or USB 1.1 that tops out at 12 Mbps.

USB 3.2 is an updated version of USB 3.1 (SuperSpeed+) and is the latest USB standard. It increases this theoretical maximum speed to 20 Gbps while USB 3.1 comes in at a maximum speed of 10 Gbps.

ICpedia is involved in many PnR projects, implementing the place and route of design blocks including floor planning, placement, clock tree building, routing, timing optimizations, DRC, LVS fixing, IR drop analysis, Formal verification, power intent checks etc.

ICpedia implements the follwoing:

Block level physical design closure in terms of timing, power, DRC/LVS etc., Physical Synthesis, Constraints validation, Floor planning, Power planning, Clock Tree Synthesis (CTS), Scan Synthesis, Scan re-order, Static Timing analysis (STA), IR, EM, Noise Analysis, and Physical Verification.