Senior Digital Design Engineer (REF: DDV04)
Responsibilities:
- RTL coding, modeling, and functional simulation of digital blocks.
- CDC/RDC/Lint analysis and fix.
- Debugging both functional and gate-level issues.
- Design synthesis, Design for Testability (DFT), and UPF constraints development.
- Performing Static Timing Analysis (STA) and resolving related issues.
- Formal verification.
- Handling libraries and technology files issues for design flows.
- Writing product specifications.
- Interacting with customer support and back-end design teams.
Qualifications
- B.Sc. in Computer/Electronics Engineering, with a 5-year minimum experience in digital design. M. Sc. is a plus.
- Solid experience in Verilog. Knowledge in SystemVerilog is a plus.
- Experience with CDC/RDC/Lint analysis (multiple clocks/resets domains design).
- Strong understanding of hardware design, timing analysis, and design verification.
- Experience with scripting languages, such as Python, Perl, or Tcl.
- Knowledge of high speed and power-aware digital design techniques is a plus.
- Good communication skills for interacting between different design groups and customer support teams.
- Must be self-motivated, proactive, and able to balance great design with meeting tight deadlines.
- Ability to produce exceptional results as an individual and team contributor.
Digital Design Engineer (REF: DDV07)
Responsibilities:
- RTL coding, modeling, and functional simulation of digital blocks.
- CDC/RDC/Lint analysis and fix.
- Debugging both functional and gate-level issues.
- Design synthesis, Design for Testability (DFT), and UPF constraints development.
- Performing Static Timing Analysis (STA) and resolving related issues.
- Formal verification.
- Handling libraries and technology files issues for design flows.
- Writing product specifications.
- Interacting with customer support and back-end design teams.
Qualifications
- B.Sc. in Computer/Electronics Engineering, with an extensive experience in digital design. M. Sc. is a plus.
- Solid experience in Verilog. Knowledge in SystemVerilog is a plus.
- Experience with CDC/RDC/Lint analysis (multiple clocks/resets domains design).
- Strong understanding of hardware design, timing analysis, and design verification.
- Experience with scripting languages, such as Python, Perl, or Tcl.
- Knowledge of high speed and power-aware digital design techniques is a plus.
- Good communication skills for interacting between different design groups and customer support teams.
- Must be self-motivated, proactive, and able to balance great design with meeting tight deadlines.
- Ability to produce exceptional results as an individual and team contributor.
Digital Verification Engineer (REF: DDV06)
Responsibilities:
- Writing complex system-level test-benches in SystemVerilog.
- Writing SystemVerilog assertions.
- Resolving functional and gate-level simulations issues.
- Debugging both functional and gate-level issues.
- Developing VMM and UVM verification environments.
- Handling libraries and technology files issues for design flows.
- Interacting with front-end design teams and customer support.
Qualifications
- B.Sc. in Computer/Electronics Engineering, with an extensive experience in digital verification. M.Sc. is a plus.
- Strong understanding of hardware design, timing analysis, and design verification.
- Good experience in Verilog and SystemVerilog.
- Hands-on experience with digital systems simulators, such as VCS.
- Good experience in writing complex test-cases, including constrained random tests.
- Good experience in writing SystemVerilog assertions.
- Familiarity with verification methodologies and environments, e.g., VMM and UVM.
- Experience in CDC/RDC/Lint analysis.
- Good experience in scripting languages, such as Python, Perl, or Tcl.
- Knowledge of SERDES concepts and serial protocol standards is a plus.
- Knowledge of high speed and power-aware digital design techniques is a plus.
- Self-motivated, proactive, and able to balance great output with meeting tight deadlines.
- Ability to produce exceptional results as an individual and team contributor.
- Good communication skills for interacting between different design groups and customer support teams.
AMS Verification Engineer (REF: AMS06)
Responsibilities:
- Work with the design team to construct self-checking testbenches to verify transistor-level circuits.
- Work with verification team on developing mixed-signal verification environment to validate complete systems.
- Verify transistor-level circuits in complete systems.
- Develop scripts to automate the verification flow.
- Interact with several teams, including analog and digital design, digital verification, and back-end design teams.
Qualifications
- B.Sc. in Electronics Engineering.
- Strong background in analog circuit concepts and design.
- Hands-on experience with SPICE simulators, such as HSPICE and XA, and simulators options.
- Hands-on experience with digital systems simulators, such as VCS.
- Excellent debugging skills.
- Experience in HDL, such as Verilog. Knowledge in SystemVerilog is a plus.
- Experience with scripting languages, such as Python, Perl, or Tcl, is a plus.
- Familiarity with verification methodologies and environments, such as VMM, is a plus.
- Knowledge of SERDES concepts and circuits is a plus.
- Must be able to work independently besides being a good team player.
- Self-motivated, proactive, and able to balance great output with meeting tight deadlines.
- Excellent command of written and spoken English language is a must.
- Good communication skills for interacting between different design groups and customer support teams.
Digital Implementation Engineer (REF: PnR01)
Responsibilities:
- Developing and maintaining the digital backend design of a variety of mixed-signal IPs and Testchips.
- Logic synthesis, DFT implementation.
- Floorplanning and Power planning.
- Placement, Clock tree Synthesis, and Routing.
- Parasitic Extraction, Static timing analysis, different timing requirements necessary for proper operation of digital systems.
- Physical verification to ensure meeting foundry design rules (DRC), LVS, and antenna checking.
- Understanding electromigration and IR drop analysis, their importance for proper operation, checking and how to fix/avoid related violations.
- Marinating design flows to meet technology dependent requirements and customer specifications.
- Interface with the larger product team to understand design constraints, deliverable formats, customer requirements.
Qualifications
- B.Sc. in Computer/Electronics Engineering with 0-2 years of industrial digital ASIC design.
- Good scripting skills for: TCL, PERL or Python, Make, Shell scripting.
- Strong problem solving and analysis abilities.
- Knowledge of physical implementation and verification tools is preferable. [Design Compiler, ICC/ICC2, PrimeTime, ICV/Calibre, Redhawk]
- Excellent command of written and spoken English language.
- Excellent verbal and written communication skills for interacting between with different design groups and customer support teams.
- Self-motivated, disciplined, proactive, and able to balance great output with meeting tight deadlines.
- Ability to produce exceptional results as an individual and team contributor.